Current efforts towards decreasing the size of transistor devices have resulted in attempts to fabricate FETs having increasingly shorter channel lengths. As FET channels approach the micron and submicron range, however, the resulting devices exhibit undesirable operating characteristics. These undesirable characteristics include, but are not limited to: 1) decreased breakdown voltage, 2) decreased punch-through voltage, 3) degraded threshold voltage control, and 4) hot-electron induced degradation.
Responsive to the above-described problems, various changes have been made to the FET structures particularly to the source and drain region structures proximate the device channel. U.S. Pat. No. 4,366,613 to Ogura et al., assigned to the assignee of the present invention, shows the use of a lightly doped drain (LDD) structure for increasing the breakdown voltage and inhibiting hot-electron induced degradation in short channel devices. This LDD structure consists of lightly doped extensions of the source and drain regions, of same conductivity type as the source and drain regions, into the channel region.
"A Half-Micron MOSFET Using Double Implanted LDD", by S. Ogura et al., 1982 IEDM Technical Digest, page 718, shows an FET including pockets (or "halos") surrounding the LDD drain and source extensions in the vicinity of the device channel, these pockets being of opposite conductivity type to the LDD extensions. Similar halos are shown in U.S. Pat. No. 4,636,822 to Codella et al., assigned to the assignee of the present invention, and in U.S. Pat. No. 4,597,824 to Shinada et al. In operation, these halos function to reduce undesirable short channel effects, including decreased threshold voltage and decreased punchthrough voltage.
Japanese Kokai No. 58-194,367 shows an FET including both LDD source and drain extensions, and a single pocket surrounding the source LDD extension. A process is shown for forming the device, the process requiring at least one highly accurate photolithographic masking step.
Japanese Kokak No. 58-115,863 shows an FET including a buried, high-dopant concentration region underlying the source and drain region, and at least one pocket surrounding the drain region, or pockets surrounding both the source and drain region.
As discussed above, the shortening of the FET channels, and the providing of subsequently smaller, more densely packed devices comprises a priority in the field. This is evidenced by the above-described publications directed to just such ends. Such accomplishments, particularly when achieved without the concomitantly expected degradations in operating performance, provide a significant contribution to the art.
An object of the present invention is to provide a new and improved FET and a method of fabricating the same.
Another object of the present invention is to provide such a FET having a sub-micron gate length and improved operating characteristics relative to the prior art.
A further object of the present invention is to provide a method for fabricating the above-described FET having a sub-micron gate length and an asymmetrical structure in the FET channel region.
In accordance with one aspect of the present invention there is provided a field effect transistor of asymmetrical structure comprising: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; and a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region.
In accordance with another aspect of the invention there is provided a field effect transistor of asymmetrical structure comprising: a semiconductor substrate of first conductivity type; source and drain regions of second conductivity type disposed in a surface of the substrate and spaced apart by a channel region; a single halo region generally surrounding the source region in the substrate, the halo region of the first conductivity type and of a higher dopant concentration than the substrate; and a single lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region.
In accordance with another aspect of the invention there is provided a method of forming a field effect transistor, comprising the steps of: providing a semiconductor substrate of first conductivity type; forming source and drain regions of second conductivity type in a surface of the substrate and spaced apart by a channel region; and forming a single, lightly doped extension of the drain region into the channel, the extension being of the second conductivity type and of a lower dopant concentration than the drain region.
In accordance with yet another aspect of the present invention, there is provided a method of forming a field effect transistor, comprising the steps of: providing a semiconductor substrate of first conductivity type; forming a generally conformal layer of gate electrode material over the device region; forming a mask over the layer of gate electrode material, the mask including a generally vertical edge situated over the substrate; forming a first device region in a portion of the substrate self-aligned with the mask; using the mask to define a gate electrode from the layer of gate electrode material while exposing a previously masked portion of the substrate adjoining the gate electrode; and forming a second device region in the newly exposed portion of the substrate self-aligned with the gate electrode.